pointed complex meaning in Chinese
有点复形
Examples
- The thesis concludes that spectrum scan speed can reach 680mhz / s at 1khz frequency resolution when it has 8192 points complex data
本文研究指出，谱分析数据量为8192点复数据时， 1khz频率分辨率要求下的扫描速度可达680mhz s以上。 - ( 3 ) design the fast calculation of modulus of 16 bit fix - point complex number and time logic of pulse compression system based on fpga ( ep1k100qc208 )
( 3 )基于fpga ( ep1k100qc208 )的16位定点复数的快速求模设计及系统时序和控制逻辑设计。 - In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ) . processor and uart ( universal asynchronous receiver transmitter ) , these cores are used in this dissertation , fpu is used for floating point complex fft processor , uart is used for fft processor " s peripheral and our test platform . in chapter 6 we discuss the design for testability , including atpg , bist and jtag method , discuss the different verification and simulation strategy in soc scale facing to different modules , build up the test platform which is used to test high performance application specified digital signal processing processor . in chapter 7 we summarize the research results and creative points , and point out the further work need to do in the future
第五章提出了基于ieee754浮点标准的浮点运算处理器的设计和异步串行通信核的设一浙江大学博士学位论文计，提出了适合硬件实现的浮点乘除法、加减运算的结构，浮点运算处理器主要用于高速fft浮点处理功能，异步串行通信核主要用于pft处理器ip核的外围扩展模块以及本文所做的验证测试平台中的数据接口部分第六章提出了面向系统级芯片的可测试性设计包括了基于扫描测试atpg 、内建自测试bist 、边界扫描测试jtag设计，在讨论可测试性设计策略选择的问题上，提出了针对不同模块进行的分别测试策略，提出了层次化jtag测试方法和扫描总线法，提出了基于fpga - In the latter , firstly the fact that digital pulse compressing technology is one of the most important ways of signal processing in modern radar is introduced . the module of 4096 - point complex fft / ifft play a very important role in ha rdware implementation of digital pulse compressing system . secondly the basic theory of radix - 4 fft and the hardware implementation based on fpga of the 4096 - point complex fft / ifft is illustrated in detail
在第二部分中，首先说明了数字脉压技术是现代雷达中重要的信号处理技术之一，而4096点fft变换模块就是硬件实现脉压技术的核心部分，然后说明了基4fft的基本知识以及基于fpga的详细的硬件实现方案。 - The system - controlled iir filter and fft were realized using fpga in this paper , and modified pipeline structure is adopted to greatly raise the running speed in the system - controlled iir filter . in the same time , it is used that the algorithm of n - point complex to compute 2n - point real data block in the radix - 2 fft . it is different to the normal method in the adoption of pipeline single dual ram for each stage
论文用fpga实现了系统的受控iir滤波器和fft部分，受控滤波器采用改进的流水线结构，运行速度得到了大幅度的提高，同时运用n点复数dft算法来计算2n点实数数据，在fpga中实现了基2的1024点复数fft ，同一般的实现不同，采用了流水线式的每级单个双口ram的方法，节省了ram的容量，经验证，该设计符合滤波器系统的要求。